Beam blanker driver system and method

ABSTRACT

A particle beam lithography system and method of blanking a beam such as a particle or other beam. The system may include a frequency divider adapted to convert a master clock signal at a first frequency into an integral number N of waveforms at a second frequency, a reference device adapted to provide a fixed threshold reference signal, a sequencer adapted to provide N sets of data, a blanking circuit for each of the waveforms for creating a blanking signal for each of the waveforms, and a logic circuit for combining each of the blanking signals from each of the blanking circuits. The blanking circuit may include a digital to analog converter adapted to receive one of the N sets of data from the sequencer and to generate a variable threshold reference signal and a window comparator adapted to receive one of the waveforms, the fixed threshold reference signal, and the variable threshold reference signal and to generate a blanking signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to blanker driver system andmethod for beams such as particle or other beams. It more particularlyrelates to a blanker driver system and method, which may be used forsystems such as particle beam lithography.

2. Background Art

There is no admission that the background art disclosed in this sectionlegally constitutes prior art.

In a particle beam based pattern writing system, the writing processinvolves exposing a sample to the beam. A mechanism of blanking the beamis incorporated for situations in which it is required that the samplenot be exposed to the beam. The writing process typically involvesexecuting a sequence of consecutive exposure intervals, synchronized toa master clock. During each of the exposure intervals, the beam may beblanked or exposed for a programmable period of time. Precise, highresolution control of the exposure time within each interval is requiredin order to ensure high fidelity of the written pattern. High resolutiondelay lines, combined with appropriate logic circuitry are typicallyused to implement such timing control circuitry. However, this approachhas several disadvantages, such as overcoming the inherent asynchronousdelay associated with such devices, as well as the limited ability toscale such an implementation to medium-high speed clock rates, e.g. onthe order of 1 GHz master clock frequency.

Variable-width pulses in a system with fixed interval timing can begenerated by using a high frequency clock, whose period is much shorterthan the fixed interval period, in combination with some counter logic.The logic can be programmed to provide an output pulse of a widthequivalent to a programmable number of periods of the high-frequencyclock. This approach does not extend to high resolution pulse widthcontrol, e.g. in order to achieve a timing resolution such as a 2.5picoseconds timing resolution, because a high-frequency clock of 400 GHzwould be required, and would be impractical.

At higher frequencies, delay lines are typically used, again inconjunction with some gating logic. The reference exposure clock can becombined with a delayed version of itself to generate a variable widthpulse. A typical example of the use of delay lines is shown in FIG. 1.

Commercially available programmable delay lines are available withresolution on the order of 10 picoseconds steps. However there areseveral problems with this approach.

In a pattern writing instrument, successive exposure times areindependently variable. Thus a programmable delay line device used inthe manner described above must be reprogrammed between exposure clocks.Considering the various timing considerations associated with thisprogramming process (setup, hold, and propagation delay of severalnanoseconds) it is clear that a single delay line cannot be used togenerate arbitrarily programmable delays on successive clock cycles.Thus a “ping-ponging” approach must be used with appropriate logic toswitch between alternate delay lines. Furthermore, the number ofadditional delay lines required depends on the absolute delay throughthe device compared to the exposure clock period.

Resolution of 10 picoseconds is inadequate to achieve the level ofexposure timing control required in the next generation of high speedmask writing instruments. For example if the exposure clock period is2.5 nanoseconds, and a Minimum Blanking Interval between successiveexposures is 20%, then 0.5 nanoseconds is reserved, and the resolutionof exposure control using a typical state-of-the-art delay line would be10 picoseconds/2.0 nanoseconds which equals 1 part in 200, or 0.5%.Performance targets for the next generation of high speed mask writinginstruments indicate that this is inadequate.

The minimum absolute delay through a typical delay line device is on theorder of several nanoseconds. In a synchronous system with a masterexposure clock, special timing adjustments must be made in order tocompensate for this asynchronous minimum delay through the device.Furthermore, if multiple delay line devices are required, as indicatedabove, then part-to-part skew must also be calibrated out.

As gating logic is required to combine the leading edge of one signalwith the falling edge of another in order to generate the variablepulse-width (FIG. 1), the output pulse-width is susceptible to timingjitter between the two different paths taken prior to combination.

A problem exists in creating blanking signals for the beam of a particlebeam column when increasing the flash rate for the next generation ofbeam lithography devices. A system and method is needed to create theblanking circuit to overcome these difficulties.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of this invention and the manner of attaining them willbecome apparent, and the invention itself will be best understood byreference to the following description of certain embodiments of theinvention taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a timing diagram of an example of a prior art delay line;

FIG. 2 is an embodiment of a blanking circuit for a particle beamlithography device according to the present invention;

FIG. 3 is a timing diagram for the blanking circuit of FIG. 2; and

FIG. 4 is a flow chart of an embodiment of a method of creating ablanking signal line for a particle beam column according to the presentinvention.

DESCRIPTION OF CERTAIN EMBODIMENTS OF THE INVENTION

It will be readily understood that the components of the embodiments asgenerally described and illustrated in the drawings herein, could bearranged and designed in a wide variety of different configurations.Thus, the following more detailed description of the embodiments of thesystem, components and method of the present invention, as representedin the drawings, is not intended to limit the scope of the invention, asclaimed, but is merely representative of the embodiments of theinvention.

A system and method is disclosed for blanking a beam such as a particleor other beam. According to an embodiment of the invention, thedisclosed blanker circuit may include a frequency divider adapted toconvert a master clock signal at a first frequency into an integralnumber N of waveforms at a second frequency, a reference device adaptedto provide a fixed threshold reference signal, a sequencer adapted toprovide N sets of data, a waveform blanking circuit for each of thewaveforms for creating a blanking signal for each of the waveforms, anda logic circuit for combining each of the blanking signals from each ofthe waveform blanking circuits. The waveform blanking circuit mayinclude a digital to analog converter adapted to receive one of the Nsets of data from the sequencer and to generate a variable thresholdreference signal and a window comparator adapted to receive one of thewaveforms, the fixed threshold reference signal, and the variablethreshold reference signal and to generate a blanking signal.

In accordance with another disclosed embodiment of the invention, thereis provided a method of generating a blanking signal line for a particlebeam column having a clock at frequency f comprising generating anintegral number N of waveforms each having a frequency of f/N;generating a fixed threshold reference signal; generating a variablethreshold reference signal for each of the waveforms; creating ablanking signal for each waveform using the specific waveform, the fixedthreshold reference signal, and the variable threshold reference signalfor the specific waveform; and combining the blanking signals for eachof the waveforms to create the blanking signal line.

According to another aspect of a disclosed embodiment of the invention,there is provided a system for generating a blanking signal line for aparticle beam column having a clock at frequency f, comprising means forgenerating an integral number N of waveforms each having a frequency off/N; means for generating a fixed threshold reference signal; means forgenerating a variable threshold reference signal for each of thewaveforms; means for creating a blanking signal for each of thewaveforms using the waveform, the fixed threshold reference signal, andthe variable threshold reference signal for the specific waveform; andmeans for combining the blanking signals for each of the waveforms tocreate the blanking signal line.

Referring to FIG. 2, an embodiment of a blanking circuit is shown. Theblanking circuit 10 may include a waveform creating device 12, asequencer 14, a DC voltage reference generator 16 providing a fixedthreshold reference signal, a plurality of band-pass filters 18, aplurality of digital to analog converters (DAC) 20 for generating aplurality of variable threshold reference signals, a plurality of windowcomparators 22, and a logic device 24.

The waveform creating device 12 may generate an integral N of waveformsusing the master exposure clock having a frequency of f. The masterexposure clock frequency f may be the rate at which output pulses are tobe generated. The frequency of each of the waveforms may be f/N. Thewaveforms may be delayed from one another by a phase difference of 2π/N,such that individual waveforms may have phase delays of 2π/N, 2*2π/N, .. . (N−1)* 2π/N, respectively. These waveforms are shown asφ_(1(Clock/N)) . . . φ_(N(Clock/N)).

The sequencer 14 may provide digital pulse timing data to each of theDACs 20 a clock rate of f/N. The data may contain the value for each ofthe variable threshold reference signals and timed to allow eachvariable threshold reference signal to settle prior to its use as areference signal.

Each of the N waveforms may include a waveform blanking circuit that mayinclude one of the band-pass filters 18, one of the DACs 20, and one ofthe window comparator circuits 22. The band-pass filter 18 may be usedto generate a clean sine waveform of frequency f/N. The DAC 20 mayreceive digital pulse timing data at a clock rate of f/N, therebygenerating a synchronous variable voltage threshold. The windowcomparator circuit 22 may generate a pulse or blanking signal for thetime during which the instantaneous voltage level of the clean sinewaveform exceeds the voltage at the output of the DAC, i.e. the variablethreshold, but is less than the voltage reference, i.e. the fixedthreshold.

The logic device 24 may combine the individual pulses or blankingsignals from each of the N waveform blanking circuits into an outputstream that provides pulses at an aggregate rate of master clockfrequency f. These pulses may establish the exposure times for the beamcolumn. An arbitrary minimum blanking interval between successive pulsesmay be established.

Referring now to FIG. 3, a timing diagram for the blanking circuit ofFIG. 2 is shown. The sine waveform φ1 may be applied to a high speedwindow comparator with upper limit V_(Fixed) _(—) _(Threshold) providedby the DC voltage reference generator and lower limit V_(variable) _(—)_(Threshold) provided by the DAC 20 for waveform φ1. Intermediate signalBlank (φ1) may transition to a low state when sine waveform φ1 exceedsthe variable threshold voltage, but is less than the fixed thresholdvoltage. Intermediate signal Blank (φ1) may transition to a high statewhen sine waveform φ1 exceeds the fixed threshold voltage. Some timeafter the sine waveform φ1 exceeds the fixed threshold voltage, thevariable threshold for waveform φ1 may be changed to a new value andallowed to settle while blank pulses for waveforms φ2, φ3, and φ4 may begenerated by similar circuits. Note that in this manner, the settlingtime requirement for the variable threshold DAC to reach the desiredvalue may be extended to (N−1)/f. Then the next Blank (φ1) signal may begenerated. Output logic may combine signals Blank(φ1), Blank(φ2),Blank(φ3), and Blank(φ4) to generate the output signal Blank as shown.

The following discussion calculates the achievable timing resolution forthe circuit of FIG. 2. Since the sine waveform is non-linear, thedifferential timing resolution (ΔT) for an incremental change in DACvalue (ΔV) may vary over the range of available DAC values. The worstcase timing resolution occurs where the slope of the sine wave is at aminimum. Thus the worst case timing resolution achievable (ΔT_(max)) maybe determined by calculating the time difference between the minimumthreshold amplitude and the minimum threshold value plus one leastsignificant bit (LSB).

The calculation for the relevant angular information for sine waveformsis as follows:

-   -   The phase delay between waveforms is 2π/N radians.    -   If no minimum blanking interval is imposed, the active portion        used for timing control for a given sine waveform is −π/N to        +π/N.    -   Allowing a minimum blanking interval to be imposed between        successive pulses, let the percentage of the clock period that        can be actively utilized be denoted by variable A. For example,        if the minimum blanking interval is 20%, then the active portion        of the output period is 80%, and A=0.8.    -   The active portion of a given sine waveform is then: −Aπ/N to        +Aπ/N.

The calculation of the amplitudes corresponding to the minimum andmaximum thresholds, and amplitude of one LSB of the variable thresholdDAC may be as follows:

-   -   Amplitude for Minimum Threshold=sin(−Aπ/N)    -   Amplitude for Maximum Threshold=sin(+Aπ/N)    -   For a Variable Threshold DAC with a resolution of n bits, the        amplitude of 1 LSB is given by: $\begin{matrix}        {{{LSB}\quad{Amplitude}} = {\frac{1}{2^{n}}\left( {{\sin\left( {+ \frac{A\quad }{N}} \right)} - {\sin\left( {- \frac{A\quad }{N}} \right)}} \right)}} \\        {= {\frac{1}{2^{n}}\left( {2\quad{\sin\left( \frac{A\quad }{N} \right)}} \right)}} \\        {= {\frac{1}{2^{n - 1}}\left( {\sin\left( \frac{A\quad }{N} \right)} \right)}}        \end{matrix}$

Next, the calculation of the angular displacement between the (MinimumThreshold) and the (Minimum Threshold+1 LSB) to find the worst casetiming resolution ΔT_(max) is as follows:

-   -   The angular displacement corresponding to the Min Threshold=ωt₁        and ωt₁=−Aπ/N radians.    -   The angular displacement corresponding to (Min Threshold        amplitude plus one LSB) of the Variable Threshold DAC is:        $\begin{matrix}        {\left. {{\omega\quad t_{2}} = {{\sin^{- 1}\left( {- \frac{A\quad }{N}} \right)} + {\frac{1}{2^{n - 1}}{\sin\left( \frac{A\quad }{N} \right)}}}} \right)\quad{radians}} \\        {= {{\sin^{- 1}\left( {\left( {\frac{1}{{2\quad n} - 1} - 1} \right){\sin\left( \frac{A\quad }{N} \right)}} \right)}\quad{radians}}}        \end{matrix}$    -   Then, subtracting ωt₁ from the above equation gives the        following: $\begin{matrix}        {{\omega\left( {t_{2} - t_{1}} \right)} = {{\sin^{- 1}\left( {\left( {\frac{1}{{2\quad n} - 1} - 1} \right)\sin\left( \frac{A\quad }{N} \right)} \right)} - \left( {- \frac{A\quad }{N}} \right)}} \\        {\left( {t_{2} - t_{1}} \right) = \frac{\left( {\left( \frac{A\quad }{N} \right) + {\sin^{- 1}\left( {\left( {\frac{1}{2^{n - 1}} - 1} \right){\sin\left( \frac{A\quad }{N} \right)}} \right)}} \right.}{\omega}}        \end{matrix}$    -   Substituting for ω=2πf/N results in the following equation:        ${\Delta\quad T_{\max}} = \frac{\left( {\left( \frac{A\quad }{N} \right) + {\sin^{- 1}\left( {\left( {\frac{1}{2^{n - 1}} - 1} \right){\sin\left( \frac{A\quad }{N} \right)}} \right)}} \right.}{2\quad{\left( \frac{f}{N} \right)}}$

As an example, for the case of: Sine wave amplitude scaled to ±1 MasterClock Frequency: 400 MHz Divisor N 4 Minimum Blanking Interval 20%Variable Threshold DAC resolution 10 bits

The worst case timing resolution for this example may be given as:$\begin{matrix}{{\Delta\quad T_{\max}} = \frac{\left( {\left( \frac{A\quad }{N} \right) + {\sin^{- 1}\left( {\left( {\frac{1}{2^{n - 1}} - 1} \right){\sin\left( \frac{A\quad }{N} \right)}} \right)}} \right.}{2\quad{\left( \frac{f}{N} \right)}}} \\{= \frac{\left( \left( {\frac{0.8\quad }{4} + {\sin^{- 1}\left( {\left( {\frac{1}{2^{10 - 1}} - 1} \right){\sin\left( \frac{0.8\quad }{4} \right)}} \right)}} \right. \right.}{2\quad{\left( \frac{400 \times 10^{6}}{4} \right)}}} \\{= {2.26\quad{picoseconds}}}\end{matrix}$

Using this worst case timing resolution, the worst case resolution ofexposure control using this example would be 2.26 picoseconds/2.0nanoseconds or approximately 0.1%.

The amplitude sensitivity of one LSB of the variable threshold DAC maybe ½^(n) of the full scale sine wave amplitude. Therefore the overallsignal to noise ratio (SNR) requirement may be on the order of 2^(n):1.

Considering the example given above where ΔT_(max)=2.26 picoseconds maybe achieved for a DAC of n=10. Placing a requirement for the circuitnoise to be less than ½ LSB, then the required SNR equals 2048:1. Thissignal to noise ratio may be achieved since the fixed voltage referencemay be a DC voltage that may be heavily low-pass filtered, the variablethreshold DAC output may be filtered at approximately f/N and that thepass-band of the band-pass filter applied to the sine waveform may bekept to a minimum.

In addition to the benefit that the relative insensitivity to noiseprovides to jitter performance, the concept may provide another means ofreducing the output timing sensitivity to circuit jitter. Though small,there may be some relative timing jitter between the N waveforms φ₁, . .. φ_(N) with respect to the master exposure clock frequency f. Note thatif waveform φ_(N) has a timing displacement with respect to the masterexposure clock due to some long-term timing jitter, then the leading andtrailing edges of the resulting blanking pulse may be offset by thisamount. Thus the absolute placement of the resulting output pulse withinthe exposure interval may be displaced as a result of this jitter;however the pulse width, which may be of primary importance as itcontrols exposure time, may be unchanged. Short-term jitter over thetime for one clock phase may be small.

As described above, the settling time requirement for the variablethreshold DAC to reach the desired value may be extended to (N−1)/f. Forexample, in the case of f=400 MHz and N=4, then t_(setting)=7.5nanoseconds. This settling time may be achieved with severalcommercially available DACs, e.g. (a) Rockwell Scientific RDA012, 12-bit1 GS/s DAC; (b) Fujitsu MB86064, 14-bit, 1 GS/s DAC; (c) Euvis DA601,12-bit 2 GSPS DAC; (d) TelAsic TC240114-bit, 1 GSPS DAC; each of whichhave sub-nanosecond settling times.

It is envisioned that higher frequency clock or exposure rates may besupported by increasing the integral or divisor N, thereby reducing theperformance requirements for the individual sub-circuit channels inorder to ensure that each channel remains realizable with commerciallyavailable components. The resolution of the variable threshold DAC maybe varied to provide better resolution in timing control. The minimumblanking time between successive exposures may be varied. A ramp or someother well-controlled waveform may be used instead of a sine wave. Acommon fixed threshold voltage may be applied to all N channels, or anindividual reference may be used. Various techniques of generating the Nwaveform phases may be employed, e.g. generating a sine wave from adivided clock, or employing PLL circuitry to generate the differentphase waveforms.

Referring now to FIG. 4, an embodiment of a method of generating ablanking signal line for a particle beam column is shown and referencedas 200. At step 210 an integral number N of waveforms may be generatedusing a master clock having a frequency f. The frequency of each of thewaveforms may be f/N. Furthermore, each waveform may be delayed by 2π/N.A fixed threshold reference signal may be generated in step 220. At step230 a variable threshold reference signal may be generated for each ofthe waveforms.

At step 240 a blanking signal for each waveform may be created using theparticular waveform, the fixed threshold reference signal, and thevariable threshold reference signal. When the waveform becomes greaterthan the variable threshold, the blanking signal may drop to a lowstate. When the waveform further increases to become greater than thefixed threshold reference signal, the blanking signal may then go to ahigh state. Soon after the waveform increase to greater than the fixedthreshold, the variable threshold reference signal may be changed toanother value. The low state of the blanking signal may represent anexposure time for a flash period of the particle beam. The exposure timemay be the blanking time subtracted from the flash period time.

At step 250 the blanking signals for each of the waveforms may becombined to form the blanking signal line. Therefore, N blanking signalsat a frequency of f/N may be combined to form the blanking signal lineat a frequency of f.

While particular embodiments of the present invention have beendisclosed, it is to be understood that various different embodiments arepossible and are contemplated within the true spirit and scope of theappended claims. There is no intention, therefore, of limitations to theexact abstract or disclosure herein presented.

1. A beam blanker driver system, comprising: a frequency divider adaptedto convert a master clock signal at a first frequency into an integralnumber N of waveforms at a second frequency; a reference device adaptedto provide a fixed threshold reference signal; a sequencer adapted toprovide N sets of data; a waveform blanking circuit for each of thewaveforms including a digital to analog converter adapted to receive oneof the N sets of data from the sequencer and to generate a variablethreshold reference signal; and a window comparator adapted to receiveone of the waveforms, the fixed threshold reference signal, and thevariable threshold reference signal and to generate a blanking signal;and a logic circuit for combining each of the blanking signals from eachof the waveform blanking circuits.
 2. The system of claim 1, wherein thefrequency of the master clock signal is at least 400 MHz.
 3. The systemof claim 1, wherein the second frequency is equal to the first frequencydivided by N.
 4. The system of claim 1, wherein a phase differencebetween the waveforms is 2π/N.
 5. The system of claim 1, wherein eachwaveform blanking circuit includes a band-pass filter.
 6. The system ofclaim 1, wherein the waveforms are sine waveforms.
 7. The system ofclaim 1, wherein the waveforms are ramp waveforms.
 8. The system ofclaim 1, wherein the reference device is a DC voltage generator.
 9. Thesystem of claim 1, wherein the digital to analog converter includes atleast ten input bits.
 10. A method of generating a beam blanking signalline for a particle beam column having a clock at frequency f,comprising: generating an integral number N of waveforms each having afrequency of f/N; generating a fixed threshold reference signal;generating a variable threshold reference signal for each of thewaveforms; creating a blanking signal for each of the waveforms usingthe waveform, the fixed threshold reference signal, and the variablethreshold reference signal for the specific waveform; and combining theblanking signals for each of the waveforms to create the blanking signalline.
 11. The method of claim 10, wherein the frequency f is at least400 MHz.
 12. The method of claim 10, wherein a phase difference betweenthe waveforms is 2π/N.
 13. The method of claim 10, wherein creating ablanking signal includes changing the blanking signal to a low statewhen the value of the waveform increases over the variable thresholdreference signal.
 14. The method of claim 13, wherein creating ablanking signal includes changing the blanking signal to a high statewhen the value of the waveform increases over the fixed thresholdreference signal.
 15. The method of claim 13, wherein the low state ofthe blanking signal corresponds to an exposure time of the beam column.16. The method of claim 10, wherein the waveforms are sine waveforms.17. The method of claim 10, wherein the waveforms are ramp waveforms.18. The method of claim 10, wherein the blanking signal line has afrequency of f.
 19. A system for generating a blanking signal line for aparticle beam column having a clock at frequency f, comprising: meansfor generating an integral number N of waveforms each having a frequencyof f/N; means for generating a fixed threshold reference signal; meansfor generating a variable threshold reference signal for each of thewaveforms; means for creating a blanking signal for each of thewaveforms using the waveform, the fixed threshold reference signal, andthe variable threshold reference signal for the specific waveform; andmeans for combining the blanking signals for each of the waveforms tocreate the blanking signal line.
 20. The system of claim 19, wherein thefrequency f is at least 400 MHz.
 21. The system of claim 19, wherein aphase difference between the waveforms is 2π/N.
 22. The system of claim19, wherein means for creating a blanking signal includes means forchanging the blanking signal to a low state when the value of thewaveform increases over the variable threshold reference signal.
 23. Thesystem of claim 21, wherein means for creating a blanking signalincludes means for changing the blanking signal to a high state when thevalue of the waveform increases over the fixed threshold referencesignal.
 24. The system of claim 21, wherein the low state of theblanking signal corresponds to an exposure time of the beam column. 25.The system of claim 19, wherein the waveforms are sine waveforms. 26.The system of claim 19, wherein the waveforms are ramp waveforms. 27.The system of claim 19, wherein the blanking signal line has a frequencyof f.